← Watchlist▢Pillar · Silicon
Company File
TSMTSMC
Fabs every leading-edge AI chip on earth — the real bottleneck of the entire stack.
Plate I — Pillar-Purity Score
10/ 10
Every AI chip passes through. Pure-play — with geopolitics.
Methodology — How we score
Plate II — The Thesis
Why it’s on the list.
TSMC fabricates every meaningful leading-edge AI chip — Nvidia, AMD, Broadcom, Apple, Arm. Advanced-packaging (CoWoS) is the binding constraint. Geopolitics is the only asymmetric risk.
Plate III — Supply Chain
Upstream & downstream.
See the full chain plate for all 37 names.
Upstream — what feeds TSM
Plate IV — Thesis Breakers
What would invalidate this.
- Risk 01Taiwan Strait incident
- Risk 02CoWoS demand inflection breaks
Plate V — Also on the Silicon plate
Siblings by pillar.
- NVDAScore 10The king: GPUs, the CUDA moat, Mellanox networking, and the expanding software stack.
- ASMLScore 10EUV lithography monopoly; no EUV means no sub-5nm chips.
- ALABScore 10PCIe retimers and CXL connectivity — the glue chips inside every AI rack.
- CRDOScore 10Active electrical cables and SerDes for AI-rack interconnect; pure-play AI networking IC.
- AVGOScore 9Custom silicon partner to Google (TPU) and Meta (MTIA); dominant AI networking ASICs.
Close
Next earnings: 2026-07-16.
The Sunday brief decodes earnings that matter. Five minutes. Free.
Research only. Not investment advice. Do your own diligence.